Power of 2s

Thu, 20 Apr 2023 00:00:00 +0000

n	2^n
0	1
1	2
2	4
3	8
4	16
5	32
6	64
7	128
8	256
9	512
10	1,024
11	2,048
12	4,096
13	8,192
14	16,384
15	32,768
16	65,536
17	131,072
18	262,144
19	524,288
20	1,048,576

Reading notes - Designing a Video Game hardware in Verilog

Thu, 20 Apr 2023 00:00:00 +0000

Book: Designing Video Game Hardware in Verilog, Steven Hugg (2018).

2023-04-20-power-of-2s

Byte - 8 bits Nibble - 4 bits

/*
A clock divider in Verilog, using the cascading
flip-flop method.
*/

module clock_divider(
  input clk,
  input reset,
  output reg clk_div2,
  output reg clk_div4,
  output reg clk_div8,
  output reg clk_div16
);

  // simple ripple clock divider
  
  always @(posedge clk)
    clk_div2 <= reset ? 0 : ~clk_div2;

  always @(posedge clk_div2)
    clk_div4 <= ~clk_div4;

  always @(posedge clk_div4)
    clk_div8 <= ~clk_div8;

  always @(posedge clk_div8)
    clk_div16 <= ~clk_div16;

endmodule

Static timing anaysis

Setup time and hold time are timing constraints that must be met in digital circuits to ensure correct data transfer between logic elements. These constraints are important to consider in the design of synchronous digital circuits, which use a clock signal to synchronize the transfer of data between flip-flops or other storage elements.

Math on Raveen Kumar

Power of 2s

Reading notes - Designing a Video Game hardware in Verilog

Static timing anaysis