SystemVerilog, verilog and UVM notes

Reading Materials

https://www.hdlworks.com/hdl_corner/verilog_ref/items/SystemSimulationTimeFuncs.htm

<2022-07-27 Wed> Waveforms are not visible properly, “no value available error“ :verilog:blog:errors:

Fixed after running new simulation probably due to simulation not exitting properly corrupting the database.

<2022-07-27 Wed> To get current simulation time in verilog :verilog:blog:

System simulation time functions return the current simulation time.

$time;
$stime;
$realtime;

• $time returns the current simulation time as a 64-bit unsigned integer.

• $stime returns the lower 32-bits of the current simulationt time as an unsigned integer.

• $realtime returns the current simulation time as a real number.

• Example:

  $display(“Current simulation time is: “, $time);

• See also: https://www.hdlworks.com/hdl_corner/verilog_ref/items/SystemDisplayTasks.htm

<2022-07-27 Wed> How to concatenate in verilog :verilog:blog:

var = (32'h2000_0000) | {('d213 - 'd1), (14'h2013 | 14'b00_1000_0000_0000)};

<2022-07-27 Wed> Bit width issues in verilog :verilog:blog:

logic [15:0] a;
int b;

b=1024;
a = b; // is not as same as
a = 15'1024;

Snippets

`uvm_fatal(get_name(), "");

Reading

https://lsifrontend.blog.fc2.com/ https://verificationacademy.com/cookbook/uvm