https://raveenkumar.com/library/programming/vlsi/ Recent content in VLSI on Raveen Kumar Hugo en-US Raveen Kumar Fri, 17 Feb 2023 00:00:00 +0000 https://raveenkumar.com/library/programming/vlsi/simulations/ Fri, 17 Feb 2023 00:00:00 +0000 https://raveenkumar.com/library/programming/vlsi/simulations/ <p>Notes on compiling a testbench with <code>irun</code>. The file list it compiles lives in <code>irun_args_compile</code>.</p> <h2 id="add-every-new-file-to-irun_args_compile">Add every new file to <code>irun_args_compile</code></h2> <p>A new file stays out of the compile until you list it there.</p> <h2 id="dont-compile-a-file-or-directory-twice">Don&rsquo;t compile a file or directory twice</h2> <p>Listing the same file or directory twice stops the compile with one of these errors:</p> <ul> <li><code>xmvlog: *E,COFILX</code></li> <li><code>xmvlog: *E,ILLPDL</code></li> </ul> <h2 id="dont-include-a-file-that-is-already-compiled">Don&rsquo;t <code>`include</code> a file that is already compiled</h2> <p>If <code>irun_args_compile</code> already compiles a file, the <code>.sv</code> file doesn&rsquo;t need to <code>`include</code> it again.</p> https://raveenkumar.com/library/programming/vlsi/system_verilog_and_uvm/ Fri, 17 Feb 2023 00:00:00 +0000 https://raveenkumar.com/library/programming/vlsi/system_verilog_and_uvm/ <h2 id="reading-materials">Reading Materials</h2> <p><a href="https://www.hdlworks.com/hdl_corner/verilog_ref/items/SystemSimulationTimeFuncs.htm">https://www.hdlworks.com/hdl_corner/verilog_ref/items/SystemSimulationTimeFuncs.htm</a></p> <h2 id="2022-07-27-wed--waveforms-are-not-visible-properly-no-value-available-error-----verilogblogerrors"><span class="timestamp-wrapper"><span class="timestamp">&lt;2022-07-27 Wed&gt; </span></span> Waveforms are not visible properly, “no value available error“ :verilog:blog:errors:</h2> <p>Fixed after running new simulation probably due to simulation not exitting properly corrupting the database.</p> <h2 id="2022-07-27-wed--to-get-current-simulation-time-in-verilog-----verilogblog"><span class="timestamp-wrapper"><span class="timestamp">&lt;2022-07-27 Wed&gt; </span></span> To get current simulation time in verilog :verilog:blog:</h2> <p>System simulation time functions return the current simulation time.</p> <pre><code>$time; $stime; $realtime; </code></pre> <ul> <li> <p><code>$time</code> returns the current simulation time as a 64-bit unsigned integer.</p> </li> <li> <p><code>$stime</code> returns the lower 32-bits of the current simulationt time as an unsigned integer.</p>